(1) Technical Field
The present invention relates generally to semiconductor devices and more particularly to an NFET/PFET device having dual etch stop liners and silicate layers of normal thickness and resistance.
(2) Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents).
One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride liners. For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. Accordingly, a dual/hybrid liner scheme is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of a dual/hybrid barrier silicon nitride liners for stress enhancement of NFET/PFET devices, the first deposited liner must be removed in one of the two FET regions by patterning and etching. For example, FIG. 1 shows a typical device 100 comprising a buried silicon dioxide (BOX) 110, a shallow trench isolation (STI) 120, an NFET 140, a spacer 142, a PFET 150, a spacer 152, and a suicide layer 130a-d. Suicide layer 130a-d may be any material known in the art, including, for example, cobalt silicate (CoSi2), titanium silicate (TiSi2), molybdenum silicate (MoSi2), tungsten silicate (WSi2), nickel silicate (NixSiy), and tantalum silicate (TaSi2).
FIG. 2 shows the deposition of a first silicon nitride liner 160 onto device 100. In this case, first silicon nitride liner 160 is a tensile silicon nitride, although other silicon nitrides may be used, including, for example, a compressive silicon nitride. In order to form a dual/hybrid liner, a portion of first silicon nitride liner 160 must be removed from one of the FET regions. In order to ensure sufficient contact of a second deposited liner, it is preferable that first silicon nitride liner 160 be completely removed from the chosen FET region. However, complete removal of first silicon nitride liner 160 requires an over etch, necessarily resulting in some etching of underlying silicate layer 130a-d. 
Referring to FIG. 3, the masking of NFET 140 and etching of tensile silicon nitride liner 160 adjacent PFET 150 results in an etched silicate layer 132a-b adjacent PFET 150. Etching may be by any means known in the art, including, for example, anisotropic reactive ion etching (RIE).
In methods currently known in the art, a second silicon nitride liner is deposited onto device 100 after etching, resulting in silicate layers of different thicknesses adjacent NFET 140 and PFET 150. In addition to a difference in thickness, etched silicate layer 132a-b exhibits increased silicate resistance (Rs) relative to silicate layer 130a-b. 
Silicate layer 130a-b normally has a thickness between about 15 nm and about 50 nm, with a corresponding Rs between about 6 ohm/sq and about 20 ohm/sq. By comparison, etched silicate layer 132a-b may have a thickness between about 5 nm and about 40 nm, with a corresponding Rs between about 12 ohm/sq and about 40 ohm/sq.
Particularly in technologies beyond 90 nm, which utilize very ultra small gate lengths (e.g., <35 nm) and diffusion widths (e.g., <100 nm), such an increase in Rs is unacceptable for at least two reasons. First, the increases in Rs will impact performance of the device. Second, erosion of the silicate layer during the over etch increases the chance of failure by the polysilicon conductor (PC)-opens mechanism (i.e., the silicate on top of the PC is eroded or absent).
Accordingly, a need exists for a semiconductor device having dual etch stop liners and silicate layers of normal thickness and resistance and methods for the manufacture of such a device.